In order to reduce power consumption of computer systems and computing devices, central processing units (CPUs) typically transition from an active state into an “idle” state between keystrokes, when the operating system does not have a task that needs execution by the CPU. The active state is known in the ACPI definition as the “C0” state, and the idle state refers to any other state, which consumes less power than the active state, such as “C1,” “C2,” or “C3” states. Reduced power consumption is desirable because it minimizes operating cost, avoids overheating of the components, increases time between charges, and prolongs the operating lives of batteries.
The idle state is exited when a “wakeup interrupt” occurs in the system. For example, when a peripheral, such as, an audio codec, video controller, USB controller, or storage controller requires attention by the CPU, the peripheral generates an interrupt command and the CPU undergoes a wakeup to transition back into the active state and resumes processor operation to attend to the peripheral. Even when the CPU is not receiving input from a peripheral or a user, the CPU often issues a periodic interrupt command to itself, in order to wake up at periodic intervals, such as every 20 milliseconds or so. Each time the interrupt commands are asserted, the CPU wakes up, updates a few bits, and determines if an application needs attention. If no processor operations are required by the CPU, the CPU returns to the idle mode.
As computing systems have become larger and faster, their power requirements have also increased. In systems with relatively high power requirements, the sudden transition from an idle state to the active state causes an instantaneous current surge to the CPU, and has serious adverse effects on the CPU and its power supply components. Uncontrolled current surge, which is commonly called the load-step current, have been known to result in system lockup and/or a failure of the power supply.
Moreover, the increase in power supply often causes power supply components, such as capacitors, to mechanically vibrate when the current through them changes. In fact, capacitors are especially known to vibrate when the power consumption of a CPU transitions from low power states, such as an idle state, to higher power states, such as an active state. The magnitude of vibration is exacerbated by the need for a plurality of power supply components, such as, multiple capacitors, which are generally always used in CPUs currently produced.
The plurality of power supply components used in today's computing systems will not only vibrate, but together will vibrate in phase at the frequency of the wakeup interrupt. That is, because interrupt commands are asserted and executed at regular periodic intervals, the power supply components vibrate at those regular periodic intervals. This, in turn, causes the printed circuit board (PCB) to vibrate because it is attached to the power supply components, thereby causing the PCB to act like a sounding board and produce an audible tone, which is commonly referred to as “singing capacitors.” The tone is typically noticeable and therefore, becomes an undesirable source of distraction and annoyance to the user.
FIG. 1 shows a timing diagram 100 of a representative time period during regular periodic transitions from the active and idle states in a conventional computing system. The upper graph of FIG. 1 shows times when wakeup interrupt commands 102 are asserted to cause a CPU to wakeup or return to the active (C0) state. FIG. 1 shows the assertion of five periodic wakeup interrupt commands 102, labeled A-E. The lower graph shows the CPU execution 104 of the wakeup interrupt commands 102 along the same timeline. The baseline of the CPU execution 104 graph indicates that the CPU is in an idle state, while the elevated bars of the CPU execution 104 graph indicate times when the CPU executes the interrupt commands 102 to transition to the active (C0) state and, thus, is consuming considerable power. Upon completion of the processor task, the operating system will execute a processor “idle” instruction and the CPU will return to an idle state and consume relatively less power.
The letters “Td” between the upper and lower graph stand for time delay, signifying that there is a slight time delay between the time when each of the wakeup interrupt commands 102 is asserted and the time when the interrupt commands 102 are actually executed. As FIG. 1 shows. In current wakeup processes, a uniform time delay exists between the time when an interrupt command is asserted (A-E) and the time when the interrupt command is executed. That is, the time delay (Td) between the assertion of each of the interrupt commands 102, labeled A-E, and the execution of each of the interrupt commands 102 by the CPU is always the same duration of time. Since the interrupt source may serve the purpose of filling a fixed length memory buffer or processing a certain task, the interrupt source is often periodic. The periodic wakeup resulting from the periodic interrupt source typically accumulates as an audible noise with an identifiable frequency.
It would, therefore, be desirable to be able to transition from an idle state to an active state without suffering from the drawbacks associated with conventional techniques.